The present invention relates to a semiconductor structure and a method of fabricating the same. More particularly, the present invention relates to a field effect transistor (FET) including a threshold voltage adjusted gate stack and a method of fabricating the same.
In semiconductor devices including field effect transistors (FETs), threshold voltage of the transistors has been conventionally controlled by doping an impurity into the channel region and by appropriately adjusting the dose amount. Threshold voltage control using only this technique, e.g., only through adjustment of the amount of the channel impurity, however, raises nonconformities such that an increase in the dose of the impurity to be doped into the channel region may lower ON-state current due to scattering by the impurity, may increase the Gate-Induced Drain Leakage (GIDL) current, and may increase substrate current upon application of substrate voltage. For this reason, low-power-consumption devices having a large amount of impurity doped into the channel region have occasionally resulted in a decrease in an ON-state current, and an increase in the GIDL current.
Another prior art technique that has been conventionally used to control the threshold voltage of FET devices is to fabricate a device in which different transistors, e.g., nFETs and pFETs, are formed on gate oxides that have a different thickness. That is, it is known to form a device in which the thickness of a gate oxide film of an nFET or pFET is different from that of a gate oxide film of another nFET or pFET.
In recent years, there has been another trend of using a high dielectric constant dielectric film, i.e., a high k dielectric, as the gate insulating film of FET devices. High k dielectrics are those dielectrics that have a dielectric constant that is greater than silicon oxide. Representative high k dielectrics that are useful as a gate insulating material include metal oxides such as, for example, zirconium oxide and hafnium oxide. The use of high k dielectrics as the gate insulating film of a metal oxide semiconductor field effect transistor (MOSFET) can successfully reduce the equivalent silicon oxide thickness in an electrical sense, even if the physical thickness thereof is increased relative to a silicon oxide gate dielectric. Hence, high k dielectric films when used as a gate insulating film are stable both in a physical sense and in a structural sense. This makes it possible to increase the MOS capacity for improved MOSFET characteristics, and to reduce gate leakage current as compared with the conventional devices in which silicon oxide was used as the gate insulating film.
Although high k dielectrics provide improvements over conventionally used silicon oxide as the gate insulating film in a FET device, the use of the same is not without problems. For example, FET devices including high k gate dielectrics exhibit a non-ideal threshold voltage when the device is used. Although this problem, e.g., threshold voltage shift from an ideal value, is exhibited for both pMOSFET and nMOSFET devices, it is more pronounced with nMOSFET devices.
In the prior art, various techniques including, for example, forming a threshold voltage adjusting layer interposed between the high k gate dielectric and the gate electrode have been proposed. Although such threshold voltage adjusting techniques have been proposed, threshold voltage centering still remains a challenge in such devices due to the difficulty of integrating band-edge metals for nFETs and pFETs.
Also, in prior art techniques in which a threshold voltage adjusted gate stack is provided that includes a threshold voltage adjusting layer interposed between a high k gate dielectric and a gate electrode, wet or dry etching is typically used in patterning the threshold voltage adjusted gate stacks. When wet etching is employed in patterning the threshold voltage adjusted gate stacks, an undercut of the threshold voltage adjusting layer beneath the gate electrode is observed. The undercutting of the threshold voltage adjusting layer is undesirable since it prohibits geometrically compact integration of adjacent FETs with different threshold voltage characteristics (e.g., adjacent pFETs and nFETs). The presence of such an undercut may also provide a diffusion path for unwanted atomic and molecular species (e.g., oxygen) that may ingress into the high k gate dielectric at later fabrication steps and interfere with its structure causing threshold voltage shifts.
When dry reactive ion etching is employed in patterning the threshold voltage adjusted gate stacks, its energetic reactive ions create damage in the underlying high k layer leading to an increased gate leakage and/or threshold voltage shift.
Also, in prior art techniques, a thermal sintering step is often required in order to provide a proper distribution of atoms in the threshold voltage adjusting layer and the high k gate dielectric which causes their chemical inter-bonding. Such a sintering step may require a relatively high thermal budget that undesirably affects other important properties of structural elements such as compromising thermal stability and integrity of the gate electrode, instigating undesirable diffusion of dopants, and/or creating undesirable modification in silicides that may be present in the substrate during such sintering step.
As such, there exists a need for providing a plurality of MOSFET devices including those with a high k gate dielectric and a conductive electrode in which ideal threshold voltages are maintained during operation independent of device geometry, type, and proximity. In addition, there exists a need for providing a method for fabricating such semiconductor devices and integrated circuits.